Shows / Condor Currents
Condor Currents
Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.
Episodes
- Condor Currents
UltraQuant: 4-bit KV Caching for Context-Heavy Agents
## Episode Summary In this episode, we cover: - **UltraQuant: 4-bit KV Caching for Context-Heavy Agents** (arXiv) - **Fractional Verkle Trees: A Hypertree…
- Condor Currents
Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge
## Episode Summary In this episode, we cover: - **Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge** (arXiv) -…
- Condor Currents
AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm
## Episode Summary In this episode, we cover: - **AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm** (arXiv) - **AIA: A 16nm…
- Condor Currents
SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions
## Episode Summary In this episode, we cover: - **SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions** (arXiv) - **The Price…
- Condor Currents
A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference
## Episode Summary In this episode, we cover: - **A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference** (arXiv) - **MADAR: An…
- Condor Currents
Tiara: A Programmable Line-Rate ISA for Remote Memory Access
## Episode Summary In this episode, we cover: - **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv) - **HierSVA: A Data Synthesis…
- Condor Currents
Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators
## Episode Summary In this episode, we cover: - **Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based…
- Condor Currents
Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite
## Episode Summary In this episode, we cover: - **Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite** (arXiv) -…
- Condor Currents
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
## Episode Summary In this episode, we cover: - **SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized…
- Condor Currents
NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire
## Episode Summary In this episode, we cover: - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business…
- Condor Currents
Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques
## Episode Summary In this episode, we cover: - **Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques** (arXiv) - **SPARX…
- Condor Currents
MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
## Episode Summary In this episode, we cover: - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv)…
- Condor Currents
ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing
## Episode Summary In this episode, we cover: - **ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing** (arXiv) -…
- Condor Currents
BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference
## Episode Summary In this episode, we cover: - **BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference** (arXiv) - **Multi-Segment…
- Condor Currents
AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp
## Episode Summary In this episode, we cover: - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on…
- Condor Currents
Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library
## Episode Summary In this episode, we cover: - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The…
- Condor Currents
Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures
## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures**…
- Condor Currents
RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware
## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing…
- Condor Currents
Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures
## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU…
- Condor Currents
FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling
## Episode Summary In this episode, we cover: - **FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style…
- Condor Currents
Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory
## Episode Summary In this episode, we cover: - **Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory**…
- Condor Currents
Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge
## Episode Summary In this episode, we cover: - **Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge**…
- Condor Currents
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A…
- Condor Currents
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A…
- Condor Currents
Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation
## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A…
- Condor Currents
OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization
## Episode Summary In this episode, we cover: - **OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization** (arXiv) - **TTP: A…
- Condor Currents
How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum
## Episode Summary In this episode, we cover: - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India…
- Condor Currents
Enhancing Instruction Prefetching via Cache and TLB Management
## Episode Summary In this episode, we cover: - **Enhancing Instruction Prefetching via Cache and TLB Management** (arXiv) - **ICP: Exploiting Instruction…
- Condor Currents
SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software
## Episode Summary In this episode, we cover: - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) -…
- Condor Currents
RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware
## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing…
- Condor Currents
RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe
## Episode Summary In this episode, we cover: - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe**…
- Condor Currents
SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison
## Episode Summary In this episode, we cover: - **SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison** (arXiv) - **Beyond Static…
- Condor Currents
RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
## Episode Summary In this episode, we cover: - **RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V…
Condor CurrentsOptimizing Branch Predictor for Graph Applications
## Episode Summary In this episode, we cover: - **Optimizing Branch Predictor for Graph Applications** (arXiv) - **A Comparative Analysis of ARM and x86-64…
Condor CurrentsRISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
## Episode Summary In this episode, we cover: - **RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for…
Condor CurrentsRagged Paged Attention: A High-Performance and Flexible LLM Inference Kernel for TPU
## Episode Summary In this episode, we cover: - **Ragged Paged Attention: A High-Performance and Flexible LLM Inference Kernel for TPU** (arXiv) - **Overmind…
Condor CurrentsChecking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday
## Episode Summary In this episode, we cover: - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **SpacemiT K3…
Condor CurrentsEPAC: The Last Dance
## Episode Summary In this episode, we cover: - **EPAC: The Last Dance** (arXiv) - **Strix: Re-thinking NPU Reliability from a System Perspective** (arXiv) -…
Condor CurrentsDEEP-GAP: Deep-learning Evaluation of Execution Parallelism in GPU Architectural Performance
## Episode Summary In this episode, we cover: - **DEEP-GAP: Deep-learning Evaluation of Execution Parallelism in GPU Architectural Performance** (arXiv) -…
Condor CurrentsBit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net
## Episode Summary In this episode, we cover: - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches -…
Condor CurrentsQuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society
## Episode Summary In this episode, we cover: - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE…
Condor CurrentsA Precision Emulation Approach to the GPU Acceleration of Ab Initio Electronic Structure Calculations
## Episode Summary In this episode, we cover: - **A Precision Emulation Approach to the GPU Acceleration of Ab Initio Electronic Structure Calculations**…
Condor CurrentsThroughput Optimization as a Strategic Lever in Large-Scale AI Systems: Evidence from Dataloader and Memory Profiling Innovations
## Episode Summary In this episode, we cover: - **Throughput Optimization as a Strategic Lever in Large-Scale AI Systems: Evidence from Dataloader and Memory…
Condor CurrentsHighly-Parallel Atom-Detection Accelerator for Tweezer-Based Neutral Atom Quantum Computers
## Episode Summary In this episode, we cover: - **Highly-Parallel Atom-Detection Accelerator for Tweezer-Based Neutral Atom Quantum Computers** (arXiv) -…
Condor CurrentsPer-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
## Episode Summary In this episode, we cover: - **Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System** (arXiv) - **Toward a…
Condor CurrentsCurrent RISC-V CPUs Being Too Slow Causes Headaches For Fedora: ~5x Slower Builds - Phoronix
## Episode Summary In this episode, we cover: - **Current RISC-V CPUs Being Too Slow Causes Headaches For Fedora: ~5x Slower Builds - Phoronix** (google_riscv)…
Condor CurrentsThe RISC-V Vector Extensions for AI - jonpeddie.com
## Episode Summary In this episode, we cover: - **The RISC-V Vector Extensions for AI - jonpeddie.com** (google_riscv) - **SpacemiT K3 “16-core” RISC-V SoC…
Condor CurrentsVividnode Mobile AI Packs RISC-V Processor and 60 TOPS AI Engine - LinuxGizmos.com
## Episode Summary In this episode, we cover: - **Vividnode Mobile AI Packs RISC-V Processor and 60 TOPS AI Engine - LinuxGizmos.com** (google_riscv) -…
Condor CurrentsTRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
## Episode Summary In this episode, we cover: - **TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI** (arXiv) - **2DIO: A…
Condor CurrentsTorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design
## Episode Summary In this episode, we cover: - **TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design**…
Condor CurrentsPAI: Fast, Accurate, and Full Benchmark Performance Projection with AI
## Episode Summary In this episode, we cover: - **PAI: Fast, Accurate, and Full Benchmark Performance Projection with AI** (arXiv) - **TurboMem…
Condor CurrentsAlibaba delivers RISC-V server chip optimized to run China’s top AI models
## Episode Summary In this episode, we cover: - **Alibaba delivers RISC-V server chip optimized to run China’s top AI models** (the_register) - **TUMCREATE to…
Condor CurrentsSpacemiT K3 "16-core" RISC-V SoC system information and (early) benchmarks - CNX Software
## Episode Summary In this episode, we cover: - **SpacemiT K3 "16-core" RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) -…
Condor CurrentsAs Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - theregister.com
## Episode Summary In this episode, we cover: - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - theregister.com**…
Condor CurrentsMitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
## Episode Summary In this episode, we cover: - **Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design** (arXiv) - **SNAP-V: A RISC-V…
Condor CurrentsAn FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
## Episode Summary In this episode, we cover: - **An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural…
Condor CurrentsNVIDIA Ports CUDA to RISC-V, Betting Big on Open-Source ISA - TechPowerUp
## Episode Summary In this episode, we cover: - **NVIDIA Ports CUDA to RISC-V, Betting Big on Open-Source ISA - TechPowerUp** (google_riscv) - **China claims…
Condor CurrentsEnabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
## Episode Summary In this episode, we cover: - **Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings** (arXiv) - **RAGPerf: An…
Condor CurrentsA Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
## Episode Summary In this episode, we cover: - **A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency** (arXiv) - **Dynamic Sparse…
Condor CurrentsMachine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage
## Episode Summary In this episode, we cover: - **Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage** (arXiv) -…