SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS

Condor Currents · Oct 10, 2026

## Episode Summary In this episode, we cover: - **SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS** (arXiv) - **BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks** (arXiv) - **Nuvia Architects’ New CPU Core Can Use Arm, RISC-V or x86 - HWCooling.net** (google_riscv) - **Upbeat Technology’s Bluemag Pi Pairs RISC-V Processors and AI Inference for Advanced Flight Control - Embedded Computing Design** (google_riscv) - **Efinix® Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire™ RV64…