Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!
## Episode Summary In this episode, we cover: - **Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!** (arXiv) - **Minimum RISC-V: Maximum FPGA Efficiency** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
The skinny
The skinny isn't ready yet — notes appear once the transcript is processed.