Compiling a RISC-V CPU Into Neural Weights
Qwenputer is an experimental model by Divyansh Agrawal: Qwen3.5-4B with a deterministic 32-bit RISC-V CPU (RV32IM, plus Zba and a small bignum coprocessor) compiled directly into its weights. According to the author, no training or fine-tuning is involved: a compiler sets every weight of 11 added layers placed in front of Qwen's 32, while Qwen's own weights stay unchanged. In those layers, attention heads do memory lookups, feed-forward units do the arithmetic and logic, and Gated DeltaNet heads hold the registers, memory and program counter. The CPU's RAM is the model's own Gated DeltaNet…
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