Cache Coherence and Memory Consistency Models: MESI, MOESI, Directory-Based Mesh Interconnects, False Sharing, Sequential Consistency, TSO, and Relaxed Ordering

Deep End Era. Engineering with Sankalp · Oct 29, 2026 · 1h 3m

A lock-free queue that ran for five years without a single error on x86-64 servers crashes in ten minutes when ported to a 128-core ARMv9 or RISC-V server—even though both chips have 100% cache-coherent caches. We unpack why Cache Coherence is not Memory Consistency, tracing MESI/MOESI/MESIF state machines, directory-based 2D mesh interconnects, false sharing, x86-TSO store buffers, and acquire-release memory ordering.

Chapters

00:00:00 Opening: The Lock-Free Queue That Only Crashes off x86

00:04:28 Why Private Caches Create the Coherence Problem: The SWMR Invariant

00:08:10 The Nineteen…