Latest / Hardware Startups with Fexingo: Devices, Robotics, and Manufacturing Tech Companies / How Hardware Startups Use Boundary Scan to Test Dense Boards
Transcript
- Lucas: You're building a board with 400 pins on a BGA package, eight layers, blind vias, and the prototype comes back dead. No smoke, no shorts — just nothing. Your multimeter probes can't reach half the nets because they're buried under the package. What do you do? Luna: You cry a little, then you call in boundary scan. Lucas: Exactly. And that's what we are looking at today — boundary scan testing, also known as JTAG testing, which is the method hardware startups use when physical probing is no longer an option. It is the single most underutilized test technique in early-stage hardware, and it can save you months of debug time. Luna: Before we go deep — Lucas, we do this show ad-free because we think this kind of nuts and bolts engineering conversation should be accessible to anyone building hardware. If that matters to you, the link is buy me a coffee dot com slash fexingo. No pressure, just a way to keep it going. Lucas: Appreciate that, Luna. And it really does help. So — boundary scan. The formal name is IEEE Standard 1149.1, adopted in 1990, revised a few times since. It was originally created by the Joint Test Action Group — that's where JTAG comes from — to solve exactly the problem of testing boards with high-density packages. Luna: How does it work physically? You are not touching the pins, right? Lucas: Right. You add a small piece of logic inside every chip that supports JTAG — typically four extra pins: TDI, TDO, TCK, and TMS. Test Data In, Test Data Out, Clock, and Mode Select. These pins form a serial chain that runs through all the compliant chips on the board. The test controller sends a bit pattern through the chain, and each chip's boundary scan logic can force or capture the state of its I/O pins without the chip actually running its normal function. Luna: So you can basically inject a signal on one side of a solder joint and read it on the other side, without ever touching the joint itself. Lucas: Exactly. And that lets you test for opens, shorts, and even logic faults on nets between chips. The beauty is you don't need a bed of nails fixture with hundreds of pogo pins. You just need five connections from your test controller to the board — ground, power, and those four JTAG signals. That's it. Luna: I remember a startup I worked with — they were building a 12-layer board for a medical sensor. They had a 324-ball BGA processor and a bunch of fine-pitch connectors. First spin, the board was dead. They spent two weeks probing vias, scoping signals, getting nowhere. Then someone suggested JTAG. They wrote a simple boundary scan test in one afternoon, ran it, and found a via that was open on layer 8. They could never have found that with a scope. Lucas: That is the classic story, and it is not rare. The reason startups skip boundary scan is they think it's expensive or complicated. The hardware — a JTAG controller — costs anywhere from a hundred to a few thousand dollars. The software can be open source or commercial. For a low-volume prototype run, you can even use a cheap FTDI cable and open-source software like OpenOCD or UrJTAG. Luna: But you have to design for it from the start, right? You can't just add JTAG after the board is laid out. Lucas: That's the key point. You have to include the JTAG header and connect the boundary scan chain during PCB design. It's one extra four-pin header and a few traces. If you forget, you lose the ability entirely. But if you plan for it, you get a debug superpower. And the incremental cost is essentially zero — a header costs pennies. Luna: What about chips that don't support JTAG? Not every component has boundary scan logic. Lucas: True. Many simple components — resistors, capacitors, discrete transistors — don't have JTAG. But you can still test nets that connect from a jtag capable chip to a non jtag part by using the chip's pins to drive a pattern and then measuring at another JTAG chip on the same net. Alternatively, you add a small 'cluster test' where you treat a group of non jtag parts as a logic cloud and verify the overall function. It's not perfect, but it covers a huge percentage of the board. Luna: So the main benefit is catching manufacturing defects — opens, shorts — before you power up the board for the first time. Lucas: Right. And that's huge because a powered-up board with a short can destroy components. Boundary scan lets you test all the interconnects without applying any power to the core logic. It's a cold test. You can also use it for in-system programming — loading firmware into flash memory or configuring FPGAs over the same JTAG chain. So the same four pins serve both test and programming. Luna: I've seen startups use JTAG for programming and never realize they could also use it for structural test. They just flash the firmware and hope the board works. Lucas: Exactly. And that's a missed opportunity. Because if you have JTAG for programming, you already have the hardware. Just add a boundary scan test in your production flow. It takes a few hours to write the test vectors, and then every board gets tested before power-on. Your yield goes up, your debug time goes down. Luna: Are there limitations? I mean, what about high-speed signals? Boundary scan can't test signal integrity at gigabit speeds. Lucas: No, it cannot. Boundary scan is a DC test — it checks that the connection exists, not that it works at 10 gigabits per second. For high-speed serial links like PCIe or USB 3.0, you need additional testing like built-in self-test or loopback testing. But for the vast majority of interconnects — address buses, data buses, control signals — boundary scan is sufficient. And if the DC connection is bad, the high-speed link will fail anyway. So it's a necessary, if not sufficient, condition. Luna: So the takeaway for a hardware startup: if you are designing a board with any BGA or fine-pitch component, add a JTAG header. It costs almost nothing and gives you a powerful test capability. Lucas: Absolutely. And if you are already using JTAG for programming, spend one afternoon writing a boundary scan test. It will pay for itself the first time you catch a bad solder joint on a prototype. I have seen startups reduce their bring-up time from weeks to days. Luna: Let's talk about a specific case. I read about a startup making a drone flight controller. They had a 144-pin LQFP processor and a bunch of sensors. First batch of 50 boards, about 20 percent failed in functional test. They spent weeks debugging. Turned out there was a cold solder joint on one pin of the accelerometer. They added boundary scan, caught it in seconds, and the next batch had zero failures. Lucas: That twenty percent to zero — that is the kind of improvement that makes a startup viable. Because hardware startups cannot afford high defect rates. The margins are thin, the volumes are low, and rework is expensive. Boundary scan is one of those tools that seems like overkill until you need it, and then it's indispensable. Luna: What about software? Is there a good open-source toolchain for this? Lucas: Yeah, there are several. OpenOCD is the most popular open-source on-chip debugger, and it supports boundary scan on many chips. UrJTAG is another option. For commercial tools, XJTAG and JTAG Technologies offer more features like automatic test pattern generation. For a startup, I would start with OpenOCD and a cheap ftdi based JTAG adapter. You can get a full setup for under fifty dollars. Luna: And how do you write the test? You need a netlist, right? Lucas: You need a board netlist in a format like BSDL — Boundary Scan Description Language. Most chip manufacturers provide BSDL files for their jtag compliant parts. Your EDA tool can also export the netlist. Then the test software lets you define patterns: drive pin 3 high on chip U1, check that pin 7 on chip U2 sees a high. If it doesn't, you have an open. Or drive two pins high and check that a third isn't shorted to them. It is straightforward once you have the files. Luna: So it is a very structured, methodical process. No guessing. Lucas: Exactly. And because it is automated, you can run it on every board in production. That is much better than relying on a technician with a multimeter. Consistency matters. Luna: One more thing — what about boards without any jtag capable chips? Like a board with only discrete logic and analog parts? Lucas: Then boundary scan is not applicable. But for most modern designs with microcontrollers, FPGAs, or complex ASICs, JTAG is built in. Even many sensors and memory chips now have JTAG. So it is rare to have a board with zero JTAG. If you do, you might consider adding a small jtag capable CPLD just to provide test access. That sounds exotic, but some people do it. Luna: Alright, I think we've made the case. Add a header, use the tool, save your sanity. Lucas: And if you are a startup founder listening, and you want to see how it works in practice, there are great tutorials on YouTube and open-source projects on GitHub. The barrier to entry is very low. The biggest hurdle is awareness — knowing the tool exists. We hope this episode helps. Luna: And if you found it useful, consider supporting the show at buy me a coffee dot com slash fexingo. It helps us keep these episodes coming without ads. Thanks. Lucas: Next time, we will talk about another underutilized test technique — maybe flying probe testing for low-volume production. Until then, keep building.