Virtual Memory, Multi-Level Page Tables, TLBs, Huge Pages, and Hardware Virtualization: Radix Trees, VIPT Caches, PCID/ASID, TLB Shootdowns, EPT/Stage-2 Translation, and IOMMU

Deep End Era. Engineering with Sankalp · Oct 29, 2026 · 1h 4m

Every memory load or store in your program uses a virtual address, yet the RAM chips only understand physical addresses—and translating one to the other via a four-level page table in memory would turn every single memory access into five memory accesses. We trace virtual memory from the 1962 Manchester Atlas to VIPT caches, TLBs, PCIDs, TLB shootdowns, 24-access nested EPT walks, and IOMMU DMA remapping.

Chapters

00:00:00 Opening: When One Memory Load Quietly Turns Into Twenty-Four

00:04:12 December Nineteen Sixty-Two: Tom Kilburn, the Manchester Atlas, and the Birth of the "One-Level Store"…